1. Field of the Invention
The present invention relates to a chip package structure, and more particular, to a stacked type chip package structure.
2. Description of Related Art
In the semiconductor manufacturing industry, the production of integrated circuit (IC) devices is mainly divided into three stages including IC design, IC process and IC package.
During the IC process, a chip is manufactured by steps of wafer fabrication, IC formation, wafer sawing and so on. A wafer has an active surface, which generally refers to the surface including active devices. After the IC inside the wafer is completely formed, a plurality of bonding pads are further disposed on the active surface of the wafer such that the chip formed by sawing the wafer may be externally electrically connected to a carrier through the bonding pads. The carrier may be a lead frame or a package substrate, for example. The chip can be connected to the carrier by wire bonding or by flip chip bonding such that the bonding pads on the chip are electrically connected to contacts of the carrier, thereby forming a chip package structure.
FIGS. 1A˜1E are schematic, cross-sectional diagrams illustrating the process flow for fabricating a semiconductor device disclosed in Japanese Patent Application Publication No. 2005-317998. First, referring to FIG. 1A, a copper foil 21 is provided, which has a first patterned metallic layer 22 and a second patterned metallic layer 23 respectively formed on an upper surface and a lower surface of the copper foil 21 as electrical contacts. Referring to FIG. 1B, an etching resistance layer 24 is formed on the lower surface of the copper foil 21. Then, a half-etching process is performed on the upper surface of the copper foil 21 by using the first patterned metallic layer 22 as an etching mask so as to form a plurality of recessions R on the upper surface of the copper foil 21. Referring to FIG. 1C, a semiconductor device 11 is fixed on one of the recessions R serving as a die pad by using an adhesion layer 20. In addition, a plurality of conductive lines 16 are formed between the semiconductor device 11 and a wire bonding section 12 of the copper foil 21. Referring to FIG. 1D, a second insulating material 18 is formed on the upper surface of the copper foil 21 to encapsulate the semiconductor device 11, the conductive line 16, and the upper surface of the copper foil 21. At last, referring to FIG. 1E, a back etching process is performed on the lower surface of the copper foil 21 by using the second patterned metallic layer 23 as an etching mask for so as to form a chip package structure 10 having an area array lead.
The package structure formed by the above-mentioned method forming the die pad and the leads by etching the cooper foil is a new type of QFN package. The advantage is that the number of leads can be increased, such that the package formed by this method may meet the requirements of miniaturization and high density. However, the new type of QFN package is mainly for packaging a single chip and does not meet the current need for multi-chip module packaging.